Nonvolatile memory cell comprising a diode and a resistance-switching material

ABSTRACT

A nonvolatile memory cell is provided that includes a diode and a reversible resistance-switching element that includes a resistance-switching metal oxide or nitride, the metal oxide or nitride including only one metal. Numerous other aspects are provided.

REFERENCE TO RELATED APPLICATIONS

This application a continuation of U.S. patent application Ser. No.13/734,536, filed Jan. 4, 2013, now U.S. Pat. No. ______, which is adivision of U.S. patent application Ser. No. 12/855,462, filed Aug. 12,2010, now U.S. Pat. No. 8,349,664, which is a division of U.S. patentapplication Ser. No. 11/395,995, filed Mar. 31, 2006, now U.S. Pat. No.7,812,404, which is a continuation-in-part of U.S. patent applicationSer. No. 11/125,939, filed May 9, 2005, subsequently abandoned,hereinafter the '939 application, which is assigned to the assignee ofthe present invention and is hereby incorporated by reference in itsentirety.

This application is related to U.S. patent application Ser. No.11/394,903, “Multilevel Nonvolatile Memory Cell Comprising aResistivity-Switching Oxide or Nitride and an Antifuse,” and to U.S.patent application Ser. No. 11/395,421, “Nonvolatile Rewritable MemoryCell Comprising a Resistance-Switching Oxide or Nitride and anAntifuse,” both filed on Mar. 31, 2006, and hereby incorporated byreference in their entirety.

BACKGROUND

The invention relates to a rewriteable nonvolatile memory array in whicheach cell comprises a diode and a resistance-switching element inseries. Resistance-switching materials, which can reversibly beconverted between a high-resistance state and a low-resistance state,are known. These two stable resistance states make such materials anattractive option for use in a rewriteable non-volatile memory array. Itis very difficult to form a large, high-density array of such cells,however, due to the danger of disturbance between cells, high leakagecurrents, and myriad fabrication challenges. There is a need, therefore,for a large rewriteable nonvolatile memory array usingresistance-switching elements which can be readily fabricated andreliably programmed.

SUMMARY

The present invention is defined by the following claims, and nothing inthis section should be taken as a limitation on those claims. Ingeneral, the invention is directed to a nonvolatile memory cellcomprising a diode and a resistance-switching material.

A first aspect of the invention provides for a method for forming aplurality of nonvolatile memory cells, the method including: forming afirst plurality of substantially parallel, substantially coplanar firstconductors; forming a first plurality of diodes above the firstconductors; forming a first plurality of resistance-switching elements;and forming a second plurality of substantially parallel, substantiallycoplanar conductors above the first diodes, wherein the firstresistance-switching elements comprise a material selected from thegroup consisting of Ni_(x)O_(y), Nb_(x)O_(y), Ti_(x)O_(y), Hf_(x)O_(y),Al_(x)O_(y), Mg_(x)O_(y), Co_(x)O_(y), Cr_(x)O_(y), V_(x)O_(y),Zn_(x)O_(y), Zr_(x)O_(y), B_(x)N_(y), and Al_(x)N_(y).

A second aspect of the invention provides for a method for forming amonolithic three dimensional memory array, the method including: a)forming a first memory level above a substrate, the first memory levelformed by a method including: i) forming a first plurality of diodes;and ii) forming a first plurality of resistance-switching elementscomprising material selected from the group consisting of Ni_(x)O_(y),Nb_(x)O_(y), Ti_(x)O_(y), Hf_(x)O_(y), Al_(x)O_(y), Mg_(x)O_(y),Co_(x)O_(y), Cr_(x)O_(y), V_(x)O_(y), Zn_(x)O_(y), Zr_(x)O_(y),B_(x)N_(y), and Al_(x)N_(y), wherein each of the first diodes isarranged in series with one of the resistance-switching elements; and b)monolithically forming at least a second memory level above the firstmemory level and above the substrate.

A third aspect of the invention provides for a method for forming amonolithic three dimensional memory array, the method including: forminga first plurality of substantially parallel, substantially coplanarconductors at a first height above a substrate and extending in a firstdirection; forming a second plurality of substantially parallel,substantially coplanar conductors at a second height above the firstheight and extending in a second direction different from the firstdirection; forming a first plurality of resistance-switching elementscomprising a material selected from the group consisting of Ni_(x)O_(y),Nb_(x)O_(y), Ti_(x)O_(y), Hf_(x)O_(y), Al_(x)O_(y), Mg_(x)O_(y),Co_(x)O_(y), Cr_(x)O_(y), V_(x)O_(y), Zn_(x)O_(y), Zr_(x)O_(y),B_(x)N_(y), and Al_(x)N_(y); forming a first plurality of diodes,wherein the first diodes and the first resistance switching elements areabove the first height and below the second height; forming seconddiodes above the second conductors; and forming third conductors abovethe second conductors.

A fourth aspect of the invention provides for a method for forming anonvolatile memory cell, the method including: forming a firstconductor; forming a second conductor; forming a resistance-switchingelement; and forming a diode, wherein the diode and theresistance-switching element are disposed electrically in series betweenthe first conductor and the second conductor, and wherein, duringformation of the first and second conductors, diode, and switchingelement and crystallization of the diode, temperature does not exceedabout 500° C.

A fifth aspect of the invention provides for a method for forming amonolithic three dimensional memory array, the method including: i)forming a first memory level above a substrate, the first memory levelcomprising a plurality of first memory cells, each first memory cellcomprising: a) a resistance-switching element; and b) a diode, whereinthe temperature during formation of the first memory level does notexceed about 475° C.; and ii) monolithically forming at least a secondmemory level about the first memory level.

A sixth aspect of the invention provides for a method for programming amemory cell in a memory array, wherein the memory cell comprises aresistivity-switching layer of a metal oxide or nitride compound, themetal oxide or nitride compound including exactly one metal, the methodincluding: programming the memory cell by changing theresistivity-switching layer from a first resistivity state to a secondprogrammed resistivity state, wherein the second programmed resistivitystate stores a data state of the memory cell.

A seventh aspect of the invention provides for a method for programmingand sensing a memory cell in a memory array, wherein the memory cellcomprises a resistivity-switching layer of a metal oxide or nitridecompound, the metal oxide or nitride compound including exactly onemetal, and a diode comprising polycrystalline semiconductor material,the resistivity-switching layer and the diode arranged electrically inseries, the method including: i) applying a first programming pulse tothe memory cell wherein the first programming pulse: a) detectablychanges a first resistivity state of the resistivity-switching layer; orb) detectably changes a second resistivity state of the polycrystallinesemiconductor material, or c) detectably changes the first resistivitystate of the resistivity-switching layer and detectably changes thesecond resistivity state of the polycrystalline semiconductor material;and ii) reading the memory cell, wherein the first resistivity state ofthe resistivity switching layer serves to store data and the secondresistivity state of the polycrystalline semiconductor material servesto store data.

Each of the aspects and embodiments of the invention described hereincan be used alone or in combination with one another. The preferredaspects and embodiments will now be described with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a possible memory cell having aresistance-switching material disposed between conductors.

FIG. 2 is a perspective view of a rewriteable nonvolatile memory cellformed according to the present invention.

FIG. 3 is a perspective view of a memory level comprising cells likethose shown in FIG. 2.

FIG. 4 is an I-V curve showing the low-to-high and high-to-lowresistance conversions of nondirectional resistance-switching material.

FIG. 5A is an I-V curve showing the low-to-high resistance conversion ofdirectional resistance-switching material.

FIG. 5B is an I-V curve showing the high-to-low resistance conversion ofdirectional resistance-switching material.

FIG. 6 is a perspective view of a vertically oriented p-i-n diodepreferred in some embodiments of the present invention.

FIG. 7 is a perspective view of a vertically oriented Zener diodepreferred in other embodiments of the present invention.

FIG. 8 is an I-V curve of a p-i-n diode like the diode of FIG. 6.

FIG. 9 is an I-V curve of a Zener diode like the diode of FIG. 7.

FIG. 10 is a perspective view of an embodiment of the present inventionin which the resistance-switching material is sandwiched between noblemetal layers.

FIG. 11A is a cross-sectional view illustrating an embodiment of thepresent invention in which the resistance-switching material is notpatterned and etched.

FIG. 11B is a perspective view of a preferred embodiment of the presentinvention in which the resistance-switching material is patterned andetched with the top conductor.

FIG. 12 is a graph depicting current vs. voltage for four different datastates of a memory cell in an embodiment of the present invention.

FIGS. 13A-13C are cross-sectional views illustrating stages in theformation of a memory level of a monolithic three dimensional memoryarray formed according to a preferred embodiment of the presentinvention.

FIG. 14 is a cross-sectional view illustrating a portion of a monolithicthree dimensional memory array formed according to a preferredembodiment of the present invention.

FIG. 15 is a cross-sectional view illustrating a portion of a monolithicthree dimensional memory array formed according to a different preferredembodiment of the present invention.

FIGS. 16A-16C are cross-sectional views illustrating stages in formationof a memory level of a monolithic three dimensional memory array formedaccording to yet another preferred embodiment of the present invention.

DETAILED DESCRIPTION

A variety of materials show reversible resistivity-switching behavior.These materials include chalcogenides, carbon polymers, perovskites, andcertain metal oxides and nitrides. Specifically, there are metal oxidesand nitrides which include only one metal and exhibit reliableresistivity switching behavior, as described by Pagnia and Sotnick in“Bistable Switching in Electroformed Metal-Insulator-Metal Device,”Phys. Stat. Sol. (A) 108, 11-65 (1988). This group includes, forexample, Ni_(x)O_(y), Nb_(x)O_(y), Ti_(x)O_(y), Hf_(x)O_(y),Al_(x)O_(y), Mg_(x)O_(y), Co_(x)O_(y), Cr_(x)O_(y), V_(x)O_(y),Zn_(x)O_(y), Zr_(x)O_(y), B_(x)N_(y), and Al_(x)N_(y), where x and yrange between 0 and 1.

Examples are the stoichiometric compounds NiO, Nb₂O₅, TiO₂, HfO₂, Al₂O₃,MgO, CoO, CrO₂, VO, ZnO, ZrO, BN, and AlN, but nonstoichiometriccompounds may be used as well. A layer of one of these materials may beformed in an initial state, for example a relatively low-resistivitystate. Upon application of sufficient voltage, the material switches toa stable high-resistivity state.

This resistivity switching is reversible; subsequent application ofappropriate current or voltage can serve to return theresistivity-switching material to a stable low-resistivity state. Thisconversion can be repeated many times. For some materials, the initialstate is high-resistivity rather than low-resistance. When thisdiscussion refers to “resistivity-switching material,”“resistivity-switching metal oxide or nitride,” “resistance-switchingmemory element” or similar terms, it will be understood that areversible resistivity-switching material is meant.

These resistivity-switching materials thus are of interest for use innonvolatile memory arrays. One resistivity state may correspond to adata “0,” for example, while another resistivity state corresponds to adata “1.” Some of these materials may have more than two stableresistivity states; indeed some may be able to achieve any of aplurality of data states.

To make a memory cell using these materials, the difference inresistivity between the high-resistivity state and the low-resistivitystate must be large enough to be readily detectable. For example, theresistivity of the material in the high-resistivity state should be atleast three times that of the material in the low-resistivity state.

When this discussion refers to “resistivity-switching material,”“resistivity-switching metal oxide or nitride,” “resistance-switchingmemory element” or similar terms, it will be understood that thedifference between the low- and high-resistance or low- orhigh-resistivity states is at least a factor of three.

Many obstacles exist to using these resistivity-switching materials in alarge nonvolatile memory array, however. In one possible arrangement aplurality of memory cells are formed, each as shown in FIG. 1,comprising a resistance-switching memory element 2 (comprising one ofthe resistivity-switching materials named), disposed between conductors,for example between a top conductor 4 and a bottom conductor 6, in across-point array. A resistance-switching memory element 2 is programmedby applying voltage between the top conductor 4 and bottom conductor 6.

In a large array of such cells arranged in a cross-point array, manycells will be addressed by the same top conductor or bottom conductor.When relatively large voltage or current is required, there is dangerthat memory cells sharing a top or bottom conductor with the cell to beaddressed will be exposed to sufficient voltage or current to causeundesired resistance switching in those half-selected cells. Dependingon the biasing scheme used, excessive leakage current across unselectedcells may also be a concern.

In the present invention, a diode is paired with a resistivity-switchingmaterial to form a rewriteable nonvolatile memory cell that can beformed and programmed in a large, high-density array. Using the methodsdescribed herein, such an array can be reliably fabricated andprogrammed.

Though many embodiments are possible and an illustrative selection willbe described, a simple version of a memory cell formed according to thepresent invention is shown in FIG. 2. The cell includes a bottomconductor 200 comprising conductive material, for example heavily dopedsemiconductor material, conductive silicides, or preferably a metal, forexample tungsten, aluminum, or copper. Formed above this is a topconductor 400, which may be of the same material as the bottomconductor.

The rail-shaped top and bottom conductors preferably extend in differentdirections; for example they may be perpendicular. The conductors mayinclude conductive barrier or adhesion layers as required. Disposedbetween the top conductor 400 and bottom conductor 200 are a diode 30and a resistance-switching element 118 arranged in series. Other layers,for example barrier layers, may also be included between conductors 200and 400.

The resistance-switching element 118 is converted from thelow-resistance state to the high-resistance state, or, alternatively,from the high-resistance state to the low-resistance state, uponapplication of voltage across or flow of current through theresistance-switching element 118. The conversion from low resistance tohigh resistance is reversible.

The diode 30 acts as a one-way valve, conducting current more easily inone direction than in the other. Below a critical “turn-on” voltage inthe forward direction, the diode 30 conducts little or no current. Byuse of appropriate biasing schemes, when an individual cell is selectedfor programming, the diodes of neighboring cells can serve toelectrically isolate the resistance-switching elements of those cellsand thus prevent inadvertent programming, so long as the voltage acrossunselected or half-selected cells does not exceed the turn-on voltage ofthe diode when applied in the forward direction, or the reversebreakdown voltage when applied in the reverse direction.

A plurality of such top and bottom conductors, with intervening diodesand resistance-switching elements, can be fabricated, forming a firstmemory level, a portion of which is shown in FIG. 3. In preferredembodiments, additional memory levels can be formed stacked above thisfirst memory level, forming a highly dense monolithic three dimensionalmemory array. The memory array is formed of deposited and grown layersabove a substrate, for example a monocrystalline silicon substrate.Support circuitry is advantageously formed in the substrate below thememory array.

An advantageous method for making a dense nonvolatile one-timeprogrammable memory array which is reliably manufacturable is taught inU.S. patent application Ser. No. 10/326,470, hereinafter the '470application, since abandoned, and hereby incorporated by reference.

Related memory arrays, and their use and methods of manufacture, aretaught in U.S. patent application Ser. No. 10/955,549, “NonvolatileMemory Cell Without a Dielectric Antifuse Having High- and Low-ImpedanceStates,” filed Sep. 29, 2004 and hereinafter the '549 application, U.S.patent application Ser. No. 11/015,824, “Nonvolatile Memory CellComprising a Reduced Height Vertical Diode,” filed Dec. 17, 2004, andhereinafter the '824 application, and in U.S. patent application Ser.No. 10/954,577, “Junction Diode Comprising Varying SemiconductorCompositions,” filed Sep. 29, 2004, and hereinafter the '577application, all owned by the assignee of the present application andhereby incorporated by reference. Methods taught in these incorporatedapplications will be useful in fabricating a memory array according tothe present invention.

Fabrication Options

Preferred embodiments include several important variations. In general,the properties of the resistivity-switching material selected, and themanner in which the memory cell is intended to be used, will determinewhich embodiments are most advantageous.

Nondirectional vs. Directional Switching

In general, the resistance-switching metal oxides and nitrides namedearlier exhibit one of two general kinds of switching behavior.Referring to the I-V curve of FIG. 4, some of these materials areinitially in a low-resistivity state, in area A on the graph. Currentflows readily for applied voltage until a first voltage V₁ is reached.At voltage V₁ the resistivity-switching material converts to ahigh-resistivity state, shown in area B, and reduced current flows.

At a certain critical higher voltage V₂, the material switches back tothe initial low-resistivity state, and increased current flows. Arrowsindicate the order of state changes. This conversion is repeatable. Forthese materials, the direction of current flow and of voltage bias isimmaterial; thus these materials will be referred to as nondirectional.Voltage V₁ may be called the reset voltage while voltage V₂ may becalled the set voltage.

Others of the resistivity-switching materials, on the other hand, behaveas shown in FIGS. 5A and 5B, and will be called directional. Directionalresistivity-switching materials may also be formed in a low-resistancestate, shown in area A of FIG. 5A. Current flows readily for appliedvoltage until a first voltage V₁, the reset voltage, is reached. Atvoltage V₁ the directional resistivity-switching material converts to ahigh-resistivity state, shown in area B in FIG. 5A.

To convert directional resistivity-switching material back to thelow-resistivity state, however, a reverse voltage must be applied. Asshown in FIG. 5B, the directional resistivity-switching material ishigh-resistance in area B at negative voltage until a critical reversevoltage V₂, the set voltage. At this voltage the directionalresistivity-switching material reverts to the low-resistivity state.Arrows indicate the order of state changes. (Some materials areinitially formed in a high-resistivity state. The switching behavior isthe same; for simplicity only one initial state has been described.)

In preferred embodiments, nondirectional resistivity-switching materialsmay be paired with a substantially one-directional diode. One such diodeis a p-i-n diode, shown in FIG. 6. A preferred p-i-n diode is formed ofsemiconductor material, for example silicon, and includes a bottomheavily doped region 12 having a first conductivity type, a middleintrinsic region 14 which is not intentionally doped, and a top heavilydoped region 16 having a second conductivity type opposite the first.

In the p-i-n diode of FIG. 6, bottom region 12 is n-type while topregion 16 is p-type; if desired the polarity can be reversed. A regionof intrinsic semiconductor material like region 14, while notintentionally doped, will never be perfectly electrically neutral. Inmany fabrication processes, defects in intrinsic deposited silicon causethis material to behave as though slightly n-type. In some embodiments,it may be preferred to lightly dope this region.

Upon application of voltage, such a diode behaves as shown by the I-Vcurve of FIG. 8. Little or no current flows at very low voltage. At acritical voltage V₃, the turn-on voltage of the diode, the diode beginsto conduct and significant forward current flows. When the diode isplaced under low and moderate reverse voltages, as in area D of FIG. 8,little or no current flows; the diode acts as a one-way valve.

Upon application of very high reverse voltage V₄, however, the diodewill suffer avalanche breakdown and a reverse current will begin toflow. This event may be destructive to the diode, though ideally it isnot. Recall that both the set and reset voltages of a nondirectionalresistance switching material require current in only one direction.Thus the p-i-n diode of FIG. 6 can successfully be paired with anondirectional resistance-switching material.

As illustrated in the I-V curve of FIGS. 5A and 5B, however, forsuccessful switching, directional resistivity-switching materials mustbe exposed to both forward and reverse current. Thelow-resistivity-to-high-resistivity conversion shown in FIG. 5B requiresreverse current (at voltage V₂) Reverse current is only achieved in aone-way diode at the reverse breakdown voltage (voltage V₄ in FIG. 8),which is generally relatively high, for example at least 9 volts.

Directional resistivity-switching materials thus may not advantageouslybe paired with a one-way diode. Instead such materials may be pairedwith a reversible non-ohmic device, i.e. one that allows current flow ineither direction. One such device is a Zener diode.

An exemplary Zener diode is shown in FIG. 7. It will be seen that such adiode has a first heavily doped region 12 of a first conductivity typeand a second heavily doped region 16 of the opposite conductivity type.The polarity could be reversed. There is no intrinsic region in theZener diode of FIG. 7; in some embodiments there may be a very thinintrinsic region.

FIG. 9 shows an I-V curve of a Zener diode. The Zener diode behaves likea p-i-n diode under forward bias, with turn-on voltage V₃. Under reversebias, however, once a critical voltage V₄ is reached, the Zener diodewill allow a reverse current to flow. In a Zener diode the criticalreverse voltage V₄ is substantially lower in magnitude than that of aone-way diode.

Such a controllable reverse current at moderate voltage is required toconvert directional resistivity-switching material from thehigh-resistivity to the low-resistivity state, as described earlier andshown in FIG. 5B (at voltage V₂). Thus in embodiments of the presentinvention using directional resistivity-switching material, a Zenerdiode is preferred. (In reality, the distinction between a p-i-n diodehaving a very small intrinsic region and a Zener diode is artificial,but is made routinely by those skilled in the art.)

Nondirectional materials don't require current in both the forward andthe reverse direction, but, as described, resistivity-switching can beachieved in either direction. For some circuit arrangements, then, itmay be advantageous to pair a nondirectional resistivity-switchingmaterial with a Zener diode.

The term junction diode is used herein to refer to a semiconductordevice with the property of non-ohmic conduction, having two terminalelectrodes, and made of semiconducting material which is p-type at oneelectrode and n-type at the other. Examples include p-n diodes and n-pdiodes, which have p-type semiconductor material and n-typesemiconductor material in contact, such as Zener diodes, and p-i-ndiodes, in which intrinsic (undoped) semiconductor material isinterposed between p-type semiconductor material and n-typesemiconductor material.

High Current Requirements

To reset the resistivity-switching material, causing the transition fromthe high-resistivity to the low-resistivity state in nondirectionalresistivity-switching materials, for some materials a relatively highcurrent may be required. For these materials, it may be preferred forthe diode to be germanium or a germanium alloy, which provides highercurrent at a given voltage compared to silicon.

Noble Metal Contacts and Low Temperature Fabrication

It has been observed that resistivity switching of some of the metaloxides and nitrides mentioned earlier is more easily and reliablyachieved when the resistivity-switching material is sandwiched betweennoble metal contacts, which may be formed, for example, of Ir, Pt, Pd orAu. An example of a cell according to the present invention in whichnoble metal contacts are used is shown in FIG. 10. Resistivity-switchingelement 118 is between noble metal layers 117 and 119.

Use of noble metals poses challenges, however. When exposed to hightemperature, noble metals tend to diffuse rapidly, and may damage otherparts of the device. For example, in FIG. 10, noble metal layer 117 isadjacent to semiconductor diode 30. Extensive diffusion of a noble metalinto the semiconductor material of diode 30 will damage deviceperformance.

When the resistivity-switching element is formed between noble metalcontacts, then, it is advantageous to minimize processing temperatures.The diode may be silicon, germanium, or a silicon-germanium alloy.Germanium can be crystallized at lower temperatures than silicon, and asthe germanium content of a silicon-germanium alloy increases, thecrystallization temperature decreases. Diodes formed of germanium orgermanium alloys may be preferred when noble metal contacts are used.

Conventional deposition and crystallization temperatures ofpolycrystalline silicon (in this discussion polycrystalline silicon willbe referred to as polysilicon while polycrystalline germanium will bereferred to as polygermanium) are relatively high, rendering use ofconventionally formed polysilicon diodes incompatible with certainmetals having relatively low melting points.

For example, aluminum wires begin to soften and extrude when exposed totemperatures above about 475° C. For this reason, in many of theembodiments of the '470, '549, and '824 applications, it is preferred touse tungsten in the conductors, as tungsten wiring can withstand highertemperatures.

If germanium or a germanium alloy is used, however, the lower depositionand crystallization temperatures of germanium may allow the use ofaluminum or even copper in the conductors, for example in conductors 200and 400 of FIG. 10. These metals have low sheet resistance, and thus aregenerally preferable if the thermal budget allows their use, thoughtungsten or some other conductive material may be used instead.

Any of the teachings of U.S. patent application Ser. No. 11/125,606,“High-Density Nonvolatile Memory Array Fabricated at Low TemperatureComprising Semiconductor Diodes,” hereby incorporated by reference,which relate to low-temperature fabrication may be applicable when lowtemperatures are preferred.

Conductivity and Isolation

It has been described that to enable programming in large arrays, adiode is included in each memory cell to provide electrical isolationbetween neighboring cells. Some resistivity-switching materials aredeposited in a high-resistivity state, while others are deposited in alow-resistivity state. For a resistivity-switching material deposited ina high-resistivity state, in general, conversion to a low-resistivitystate is a localized phenomenon.

For example, referring to FIG. 11A, suppose a memory cell (shown incross-section) includes a rail-shaped bottom conductor 200, extendingleft to right across the page, a diode 30, a layer 118 ofresistivity-switching material formed in a high-resistivity state, and arail-shaped top conductor 400 extending out of the page.

In this case, the layer 118 of resistivity-switching material has beenformed as a blanket layer. So long as the high-resistivity state of thelayer 118 of resistivity-switching material is sufficiently high, layer118 will not provide an undesired conductive path, shorting conductor400 to adjacent conductors or diode 30 to adjacent diodes.

When layer 118 of resistivity-switching material is exposed to a highvoltage and is converted to a low-resistivity state, it is expected thatonly the areas of layer 118 immediately adjacent to the diode will beconverted; for example, after programming, the shaded region of layer118 will be low-resistivity, while the unshaded region will remainhigh-resistivity. The shaded regions are resistivity-switching elementsdisposed within a continuous layer 118 of resistivity-switchingmaterial.

Depending on the read, set, and reset voltages, however, for someresistivity-switching materials, the high-resistivity state of theresistivity-switching material may be too conductive for reliableisolation, and will tend to short adjacent conductors or diodes whenformed in a continuous layer as in FIG. 11A.

For different resistivity-switching materials, then, it may providedesirable to a) leave the resistivity-switching material 118unpatterned, as in the device of FIG. 11A, or b) pattern theresistivity-switching material 118 with the top or bottom conductors, asin the device of FIG. 11B (in perspective view), or c) pattern theresistivity-switching material 118 with the diode 30, as in the devicesof FIGS. 2 and 10.

When a memory element is formed of a resistivity-switching materialwhich is formed in a low-resistivity state, it must be isolated from theresistivity-switching memory element of adjacent cells to avoid formingan unwanted conductive path between them.

As described in detail in the '549 application, and in U.S. patentapplication Ser. No. 11/148,530, “Nonvolatile Memory Cell Operating byIncreasing Order in Polycrystalline Semiconductor Material,” filed Jun.8, 2005, hereinafter the '530 application and hereby incorporated byreference, for a polycrystalline semiconductor diode formed according tothe methods detailed therein, it may be expected that in someembodiments the polycrystalline of the diode will be formed in aninitial high-resistivity state, and, upon application of a sufficientlyhigh voltage, will be permanently converted to a low-resistivity state.Thus, referring to the cell of FIG. 2, when this cell is initiallyformed, both the polysilicon of diode 30 and the reversibleresistance-switching element 118 are formed in a high-resistivity state.

Upon first application of a programming voltage, both the polysilicon ofdiode 30 and the resistivity-switching element 118 will be converted totheir low-resistivity states. In general the conversion of the diode 30is permanent, while the conversion of resistivity-switching element 118is reversible. It may be desirable to perform the initial conversion ofthe polysilicon of the diodes from high-resistivity to low-resistivityin factory conditions, effectively “preconditioning” the diode.

Alternatively, U.S. patent application Ser. No. 10/954,510, “Memory CellComprising a Semiconductor Junction Diode Crystallized Adjacent to aSilicide,” filed Sep. 29, 2004, hereinafter the '510 application, whichis assigned to the assignee of the present invention and herebyincorporated by reference, describes a method to form a polycrystallinesemiconductor diode which is in a low-resistivity state as formed.

In preferred embodiments of the '510 application, the semiconductormaterial of the diode, generally silicon, is crystallized adjacent to asilicide layer, for example TiSi₂. The silicide layer provides anorderly crystallization template for the silicon as it crystallizes,resulting in a highly crystalline diode as formed, with fewercrystalline defects. This technique could be used in the presentinvention. If the diode is germanium, a germanium diode is crystallizedadjacent to a germanide layer, such as TiGe₂, which will provide ananalogous crystallization template for the germanium. The germanium ofsuch a diode will be a low-resistivity as formed, with no need for a“programming” step to create a low-resistance path through it.

One-Time Programmable Memory Cell: Two-State

A diode paired with a resistance-switching element has been described inembodiments of the present invention when used as a rewriteable memorycell. These elements can also be used in alternative embodiments to forma one-time-programmable memory cell. For nickel oxide, or any of thenamed resistivity-switching binary metal oxides or nitrides, which canswitch between lower- and higher-resistivity states, the reset switch,from a lower-resistivity to a higher-resistivity state, may prove to bethe more difficult one. (It will be understood that in this discussion“nickel oxide” may refer either to stoichiometric NiO or to anonstoichiometric compound.)

While the actual switch mechanism is unclear, it appears that a certainvoltage must be applied across the resistivity-switching layer to causeit to switch. If the set state of the material is very low-resistivity,and the material is highly conductive, it can be difficult to buildsufficient voltage to cause the switch to take place. By using thememory cell of the present invention as a one-time programmable cell,the more difficult switch can be avoided. This generally simplifiesprogramming circuitry.

One preferred resistivity-switching material, nickel oxide, isnondirectional, meaning that the material alone switches with eitherpositive or negative voltage applied. In some embodiments, though, ithas been found that, when paired with a diode, reset of a nickel oxidelayer is most readily achieved with the diode under reverse bias. Extratransistors may be required in the substrate to provide negative voltageto reverse bias the diodes. These transistors consume substrate space,making the device more expensive, and forming these transistors may addprocess complexity. Thus in embodiments in which reverse bias isrequired for reset, using the cell as a write-once cell and avoidingreset avoids the difficulties of generating negative voltage.

In the simplest way to use a memory cell comprising a diode and aresistivity-switching layer according to the present invention as aone-time programmable memory cell, the cell has two values, unprogrammedand programmed, which correspond to two distinct read currents throughthe cell.

The set voltage will vary depending on the material used for theresistance-switching element, the thickness of the layer,characteristics of the material, and other factors. Increasing the pulsetime may reduce the voltage required to set the material fromhigh-resistance to low-resistance. The set voltage may vary from, forexample, 4 volts to 10 volts.

As described earlier, if the diode is formed of polysilicon,crystallizing the polysilicon adjacent to a silicide having a latticestructure at an orientation which provides a good crystallizationtemplate for silicon will result in lower-defect, lower-resistivitypolysilicon; while crystallizing adjacent only to materials having apoor lattice match, such as titanium nitride, will result inhigher-defect, higher-resistivity polysilicon. If the diode is formed ofmore highly resistive polysilicon, application of a suitable programmingvoltage across a diode is required to convert the polysilicon to alow-resistivity state, leaving the diode with good rectifying behavior.

Further, it has been found that for some of the resistivity-switchingmetal oxides or nitrides formed in an initial high-resistivity state, insome embodiments, a forming pulse may be required to achieve the firstswitch from high to low resistivity. This forming pulse may require ahigher voltage than subsequent low-to-high or high-to-low-resistivityswitches. For example, in one trial, the forming pulse was about 8.5-9volts, while subsequent set pulses were about 6.5-7 volts.

As described in U.S. patent application Ser. No. 11/287,452, “ReversibleResistivity-Switching Metal Oxide or Nitride Layer with added Metal,”filed Nov. 23, 2005, hereinafter the '452 application and herebyincorporated by reference, adding a metal to the binary metal oxide ornitride can decrease set and reset voltages, and may decrease theamplitude of the forming pulse or eliminate the need for one entirely.

In general, the metal additive is between about 0.01 and about 5 percentof the metal atoms in the layer of metal oxide or nitride compound.Preferred metals to use for the metal additive are selected from thegroup consisting of cobalt, aluminum, gallium, indium, manganese,nickel, niobium, zirconium, titanium, hafnium, tantalum, magnesium,chromium, vanadium, boron, yttrium, and lanthanum. Thus many options arepossible for a one-time-programmable memory cell including a binarymetal oxide or nitride resistance-switching element and a diode. Theeffect of pairing the resistance-switching element with a diode of high-or low-resistivity polysilicon should be considered.

If the binary metal oxide or nitride is formed in a high-resistivitystate and the diode is formed of low-defect, low-resistivitypolysilicon, conversion of the memory cell to a programmed state, inwhich high current flows under a read voltage, is achieved by convertingthe binary metal oxide or nitride to the set state.

If the diode is formed of high-defect, high-resistivity polysilicon,however, the polysilicon of the diode must also undergo a programmingvoltage for the memory cell to behave as if programmed, allowing highcurrent flow under applied read voltage.

Depending on the relative voltages required to cause thedisorder-to-order conversion of the polysilicon and thehigh-to-low-resistivity conversion of the binary metal oxide or nitride,use of a low-defect polysilicon diode, the polysilicon crystallizedadjacent to an appropriate silicide, may be preferred.

Another alternative, if a large forming pulse is required for binarymetal oxide or nitride formed in a high-resistivity state, is to applythe forming pulse in a preconditioning step in the factory. The highvoltage required for the forming pulse can be supplied from outside ofthe die, and thus need not be available on the die.

If reverse bias is required for reset, the reset pulse can also beapplied in a further preconditioning step, so when the memory array isready for the end user, the cells are in the reset state, and can beprogrammed by the lower, post-forming set voltage. In this way circuitson the die do not need to provide either the high-voltage forming pulseor negative voltage, simplifying circuit requirements.

Further, if preconditioning forming and reset pulses are applied in thefactory, the large voltage required for a forming pulse may besufficient to convert high-defect polysilicon of the diode fromhigh-resistivity to low-resistivity. In this case, there is nodisadvantage to using a non-silicided, high-defect diode, and the extraprocess complexity of providing the silicide template layer can beavoided.

Such a memory cell in a memory array, (wherein the memory cell comprisesa resistivity-switching layer of a metal oxide or nitride compound, themetal oxide or nitride compound including exactly one metal), isprogrammed by a method comprising: programming the memory cell bychanging the resistivity-switching layer from a first resistivity stateto a second programmed resistivity state, wherein the second programmedresistivity state stores a data state of the memory cell. The memoryarray comprises circuitry to program and read the memory cell, and thecircuitry is adapted to program the memory cell no more than one time.The memory array is a one-time-programmable array.

One-Time Programmable, Multiple States

In another embodiment, it may actually be preferred to pair the binarymetal oxide or nitride with a diode formed of high-defect polysilicon.The two states of the polysilicon making up the diode, the initialhigh-resistivity state and the programmed low-resistivity state, can beused to store data, increasing the density of the memory cell.

For example, suppose a diode formed of high-defect polysilicon (notcrystallized adjacent to an appropriate silicide) is paired with a layerof nickel oxide, the two arranged electrically in series between top andbottom conductors. The nickel oxide is formed in a high-resistivitystate, requiring a forming pulse to effect the first conversion fromhigh-resistivity to low-resistivity.

Suppose the diode requires a programming voltage of 8 volts to cause thedisorder-to-order conversion described in the '530 application,converting the polysilicon to a higher-resistivity state. Supposefurther that the voltage required by the nickel oxide for the formingpulse is 10 volts. (It will be understood the voltages given here areexamples only. Voltages will change as device characteristics and otherfactors are varied.)

The memory cell as formed has high-resistivity nickel oxide and a diodeof high-resistivity polysilicon. Table 1 below summarizes three datastates that may be achieved by this memory cell. It also includes, forthis example, the programming required to attain each state, and exampleread current to be expected for each data state at an applied readvoltage of +2 volts:

TABLE 1 Read Data Polysilicon Switching current State State Layer StateProgramming at +2 V 00 High- Reset No 1 × 10⁻¹⁰ amps  resistivityprogramming 10 Low- Reset +8 V 1 × 10⁻⁸ amps resistivity 11 Low- Set +11V 1 × 10⁻⁵ amps resistivity

With no programming voltage applied, the memory cell as formed is in afirst data state, which for convenience will be called the ‘00’ state.Application of +8 volts is sufficient to convert the polysilicon of thediode from high-resistivity to low-resistivity, but is below the voltagerequired for the forming pulse, leaving the nickel oxide in its initial,high-resistivity state; this data state will be called ‘10’. Applicationof +11 volts to a cell in the initial ‘00’ state is sufficient both toeffect the disorder-to-order conversion of the polysilicon and to setthe nickel oxide to a low-resistivity state. This data state will becalled the ‘11’ state.

In another embodiment, no forming pulse, or only a small forming pulse,may be required, and the set voltage may be less than the voltagerequired to switch the polysilicon. In this case, the achievable datastates are summarized in Table 2:

TABLE 2 Read Data Polysilicon Switching current State State Layer StateProgramming at +2 V 00 High- Reset No 1 × 10⁻¹⁰ amps  resistivityprogramming 01 High- Set +6 V 1 × 10⁻⁹ amps resistivity 11 Low- Set +8 V1 × 10⁻⁵ amps resistivity

As formed, the memory cell is in the ‘00’ state, with both polysiliconand nickel oxide high-resistivity. Applying +6 volts sets the nickeloxide, but is not sufficient to switch the polysilicon, leaving the cellin the ‘01’ state. Applying 8 volts switches both the polysilicon andthe nickel oxide, leaving both in the low-resistivity states,corresponding to the ‘11’ data state.

In either of these embodiments, once the cell is in the ‘11’ state, afourth data state, in which the polysilicon of the diode is in thelow-resistivity state and the nickel oxide is in the reset state, can beachieved by resetting the nickel oxide. This state will be called the‘10’ state, and, in embodiments in which reverse bias is required forreset, is achieved by applying a negative reset pulse, say −4 volts to acell in the ‘11’ state.

To summarize, the memory cell just described is programmed by a methodcomprising i) applying a first programming pulse to the memory cellwherein the first programming pulse: a) detectably changes a firstresistivity state of the resistivity-switching layer; or b) detectablychanges a second resistivity state of the polycrystalline semiconductormaterial, or c) detectably changes the first resistivity state of theresistivity-switching layer and detectably changes the secondresistivity state of the polycrystalline semiconductor material; and ii)reading the memory cell, wherein the first resistivity state of theresistivity switching layer serves to store data and the secondresistivity state of the polycrystalline semiconductor material servesto store data. The memory cell is adapted to store one of three or fourdata states.

Multiple Resistance Levels

The resistivity-switching binary oxides or nitrides mentioned herein arecapable of attaining more than just two stable resistivity states. Insome embodiments, then, memory cells of an array formed according to thepresent invention are capable of storing more than two data states, forexample three, four, or more data states, by putting the metal oxide ornitride in one of three, four, or more detectably distinct resistivitystates. Detectably distinct data states can reliably be detected bysensing and decoding circuitry in the array. These embodiments can beeither rewriteable or one-time-programmable.

For example, suppose the resistivity-switching metal oxide or nitride isnickel oxide (it will be understood that any of the other namedmaterials may be used), which has been formed in a high-resistivitystate. Turning to FIG. 12, as formed the nickel oxide is in thelowest-resistivity state, shown on the curve labeled 00.

The nickel oxide may be put into more than two detectably distinctresistivity states. For example, a memory cell like the one shown inFIG. 2 may have four different states, each distinguished by a range ofcurrent flow under an applied read voltage, for example about 2 volts.

In this example, in the highest-resistivity state, less than about 30nanoamps of current flows when 2 volts is applied across the memorycell; this will be called the ‘00’ state. In the ‘01’ state, at 2 volts,the current will be between about 100 and 300 nanoamps. In the ‘10’state, at 2 volts, the current will be between about 1 microamp and 3microamps. In the lowest-resistivity state, the ‘11’ state, the currentat 2 volts will be more than 9 microamps. It will be understood thatthese current ranges and read voltage are supplied for clarity only;depending on the actual materials used and the characteristics of thedevice, other values may be appropriate.

In this example, a set pulse has a voltage between about 8 and about 10volts, while a reset voltage is between about 3 and about 6 volts. Inembodiments including nickel oxide paired with a p-i-n diode, the resetvoltage is applied in reverse bias. Depending on the material used andthe configuration and characteristics of the memory cell, though,reverse bias may not be required to reset the cell.

Referring to FIG. 12, the cell is formed in the ‘00’ state. To programthe cell to the 01 state, a set voltage of, for example, 8 volts may beapplied. For all set pulses a current limiter is preferably included inthe circuit. After application of the set pulse, the cell is read at 2volts.

If the current at 2 volts is in the expected range for the ‘01’ state,between about 100 and about 300 nanoamps, the cell is considered to beprogrammed. If the current is too low, (80 nanoamps, for example) anadditional set pulse, optionally at a higher set voltage, is applied,and the cell is read again at 2 volts. The process is repeated until thecurrent through the memory cell is within the correct range at 2 volts.

After a programming pulse is applied, the current may instead be abovethe acceptable range for the ‘01’ state; it may be 400 nanoamps, forexample. There are two options in this case; either a reset pulsesufficient to return the nickel oxide to the ‘00’ state can be applied,followed by another, possibly smaller, set pulse; or a reset pulse canbe applied to increase the resistivity of the nickel oxide layerslightly, moving it incrementally into the ‘01’ range. The process isrepeated until the current through the memory cell is within the correctrange at 2 volts.

A similar approach is taken to place the memory cell in the ‘10’ or ‘11’states. For example, a set voltage of 9.5 volts may be sufficient toplace the memory cell in the ‘10’ state, while a set voltage of 10 voltsmay program the memory cell to the ‘11’ data state.

The memory cell is preferably used as a rewriteable memory cell.However, it may be preferable, to save space in the substrate, to omittransistors capable of applying reverse bias, and only program the cellunder forward bias. If reverse bias is not required to reset the cell,such a memory array may be rewriteable.

If reverse bias is required for reset, however, such a memory arraycould be used as a one-time programmable array. In this case great caremust be taken never to set the cell to a state with higher current(lower resistivity of the nickel oxide layer) than desired for theintended data state. Deliberately low set voltages can be applied tolower the resistivity of the nickel oxide layer gradually and raise thecurrent into the acceptable range, avoiding ever topping the desiredrange, since in this case, with no reverse bias, this overshoot couldnot be corrected.

As in prior embodiments, the advantages or disadvantages of forming adiode of low-defect polysilicon by crystallizing the polysiliconadjacent to an appropriate silicide should be considered. If ahigh-amplitude forming pulse is required, the voltage of the formingpulse may be sufficient to convert high-defect, high-resistivitypolysilicon to lower-resistivity polysilicon; in this case the use oflow-defect, silicided polysilicon may afford no advantage. If no formingpulse or a small forming pulse is required, a diode formed oflow-defect, low-resistivity polysilicon, crystallized adjacent to anappropriate silicide, may be preferred.

If a preconditioning step, such as a forming pulse, must be applied, itmay be advantageous to perform this step in the factory. In this casethe high voltage need not be present on the die.

FIRST FABRICATION EXAMPLE

A detailed example will be provided of fabrication of a monolithic threedimensional memory array formed according to a preferred embodiment ofthe present invention. For clarity many details, including steps,materials, and process conditions, will be included. It will beunderstood that this example is non-limiting, and that these details canbe modified, omitted, or augmented while the results fall within thescope of the invention.

In general, the '470 application, the '549 application, the '824application, and the '577 application teach memory arrays comprisingmemory cells, wherein each memory cell is a one-time programmable cell.The cell is formed in a high-resistance state, and, upon application ofa programming voltage, is permanently converted to a low-resistancestate.

Specifically, teachings of the '470, '549, '824, '577 and otherincorporated applications and patents may be relevant to formation of amemory according to the present invention. For simplicity, not all ofthe details of the incorporated applications and patents will beincluded, but it will be understood that no teaching of theseapplications or patents is intended to be excluded.

Turning to FIG. 13A, formation of the memory begins with a substrate100. This substrate 100 can be any semiconducting substrate as known inthe art, such as monocrystalline silicon, IV-IV compounds likesilicon-germanium or silicon-germanium-carbon, III-V compounds, II-VIIcompounds, epitaxial layers over such substrates, or any othersemiconducting material. The substrate may include integrated circuitsfabricated therein.

An insulating layer 102 is formed over substrate 100. The insulatinglayer 102 can be silicon oxide, silicon nitride, high-dielectric film,Si—C—O—H film, or any other suitable insulating material.

The first conductors 200 are formed over the substrate 100 and insulator102. An adhesion layer 104 may be included between the insulating layer102 and the conducting layer 106 to help the conducting layer 106adhere. A preferred material for the adhesion layer 104 is titaniumnitride, though other materials may be used, or this layer may beomitted. Adhesion layer 104 can be deposited by any conventional method,for example by sputtering.

The thickness of adhesion layer 104 can range from about 20 to about 500angstroms, and is preferably between about 100 and about 400 angstroms,most preferably about 200 angstroms. Note that in this discussion,“thickness” will denote vertical thickness, measured in a directionperpendicular to substrate 100.

The next layer to be deposited is conducting layer 106. Conducting layer106 can comprise any conducting material known in the art, such as dopedsemiconductor, metals such as tungsten, or conductive metal silicides;in a preferred embodiment, conducting layer 106 is aluminum.

The thickness of conducting layer 106 can depend, in part, on thedesired sheet resistance and therefore can be any thickness thatprovides the desired sheet resistance. In one embodiment, the thicknessof conducting layer 106 can range from about 500 to about 3000angstroms, preferably about 1000 to about 2000 angstroms, mostpreferably about 1200 angstroms.

Another layer 110, preferably of titanium nitride, is deposited onconducting layer 106. It may have thickness comparable to that of layer104. A photolithography step will be performed to pattern aluminum layer106 and titanium nitride layer 104. The high reflectivity of aluminummakes it difficult to successfully perform photolithography directly onan aluminum layer. Titanium nitride layer 110 serves as ananti-reflective coating.

Once all the layers that will form the conductor rails have beendeposited, the layers will be patterned and etched using any suitablemasking and etching process to form substantially parallel,substantially coplanar conductors 200, shown in FIG. 13A incross-section.

In one embodiment, photoresist is deposited, patterned byphotolithography and the layers etched, and then the photoresistremoved, using standard process techniques such as “asking” in anoxygen-containing plasma, and strip of remaining polymers formed duringetch in a conventional liquid solvent such as those formulated by EKC.

Next a dielectric material 108 is deposited over and between conductorrails 200. Dielectric material 108 can be any known electricallyinsulating material, such as silicon oxide, silicon nitride, or siliconoxynitride. In a preferred embodiment, silicon oxide is used asdielectric material 108. The silicon oxide can be deposited using anyknown process, such as chemical vapor deposition (“CVD”), or, forexample, high-density plasma CVD (“HDPCVD”).

Finally, excess dielectric material 108 on top of conductor rails 200 isremoved, exposing the tops of conductor rails 200 separated bydielectric material 108, and leaving a substantially planar surface 109.The resulting structure is shown in FIG. 13A. This removal of dielectricoverfill to form planar surface 109 can be performed by any processknown in the art, such as etchback or chemical mechanical polishing(“CMP”).

For example, the etchback techniques described in U.S. patentapplication Ser. No. 10/883,417, “Nonselective Unpatterned Etchback toExpose Buried Patterned Features,” filed Jun. 30, 2004, hereinafter the'417 application, and hereby incorporated by reference in its entirety,can advantageously be used.

In preferred embodiments, then, bottom conductors 200 are formed bydepositing a first layer or stack of conductive material; patterning andetching the first layer or stack of conductive material to form firstconductors; and depositing dielectric fill between the first conductors.

Alternatively, conductor rails can be formed by a damascene process, inwhich oxide is deposited, trenches are etched in the oxide, then thetrenches are filled with conductive material to create the conductorrails. Formation of conductors 200 using a copper damascene process isdescribed in U.S. patent application Ser. No. 11/125,606, “High-DensityNonvolatile Memory Array Fabricated at Low Temperature ComprisingSemiconductor Diodes.” Copper damascene conductors include at least abarrier layer and a copper layer.

Next, turning to FIG. 13B, vertical pillars will be formed abovecompleted conductor rails 200. (To save space substrate 100 is omittedin FIG. 13B and subsequent figures; its presence will be assumed.)Semiconductor material that will be patterned into pillars is deposited.The semiconductor material can be germanium, silicon, silicon-germanium,silicon-germanium-carbon, or other suitable IV-IV compounds, galliumarsenide, indium phosphide, or other suitable III-V compounds, zincselinide, or other II-VII compounds, or a combination. Silicon-germaniumalloys of any proportion of silicon and germanium, for example includingat least 20, at least 50, at least 80, or at least 90 atomic percentgermanium or pure germanium may be used. The present example willdescribe the use of pure germanium. The term “pure germanium” does notexclude the presence of conductivity-enhancing dopants or contaminantsnormally found in a typical production environment.

In preferred embodiments, the semiconductor pillar comprises a junctiondiode, the junction diode comprising a bottom heavily doped region of afirst conductivity type and a top heavily doped region of a secondconductivity type. The middle region, between the top and bottomregions, is an intrinsic or lightly doped region of either the first orsecond conductivity type.

In this example, bottom heavily doped region 112 is heavily doped n-typegermanium. In a most preferred embodiment, heavily doped region 112 isdeposited and doped with an n-type dopant such as phosphorus by anyconventional method, preferably by in situ doping. This layer ispreferably between about 200 and about 800 angstroms.

Next the germanium that will form the remainder of the diode isdeposited. In some embodiments a subsequent planarization step willremove some germanium, so an extra thickness is deposited. If theplanarization step is performed using a conventional CMP method, about800 angstroms of thickness may be lost (this is an average; the amountvaries across the wafer. Depending on the slurry and methods used duringCMP, the germanium loss may be more or less.) If the planarization stepis performed by an etchback method, only about 400 angstroms ofgermanium or less may be removed.

Depending on the planarization method to be used and the desired finalthickness, between about 800 and about 4000 angstroms of undopedgermanium is deposited by any conventional method; preferably betweenabout 1500 and about 2500 angstroms; most preferably between about 1800and about 2200 angstroms. If desired, the germanium can be lightlydoped. Top heavily doped region 116 will be formed in a later implantstep, but does not exist yet at this point, and thus is not shown inFIG. 13B.

The germanium just deposited will be patterned and etched to formpillars 300. Pillars 300 should have about the same pitch and about thesame width as conductors 200 below, such that each pillar 300 is formedon top of a conductor 200. Some misalignment can be tolerated.

The pillars 300 can be formed using any suitable masking and etchingprocess. For example, photoresist can be deposited, patterned usingstandard photolithography techniques, and etched, then the photoresistremoved. Alternatively, a hard mask of some other material, for examplesilicon dioxide, can be formed on top of the semiconductor layer stack,with bottom antireflective coating (“BARC”) on top, then patterned andetched. Similarly, dielectric antireflective coating (“DARC”) can beused as a hard mask.

The photolithography techniques described in U.S. patent applicationSer. No. 10/728436, “Photomask Features with Interior Nonprinting WindowUsing Alternating Phase Shifting,” filed Dec. 5, 2003; or U.S. patentapplication Ser. No. 10/815,312, “Photomask Features with ChromelessNonprinting Phase Shifting Window,” filed Apr. 1, 2004, both owned bythe assignee of the present invention and hereby incorporated byreference, can advantageously be used to perform any photolithographystep used in formation of a memory array according to the presentinvention.

Dielectric material 108 is deposited over and between pillars 300,filling the gaps between them. Dielectric material 108 can be any knownelectrically insulating material, such as silicon oxide, siliconnitride, or silicon oxynitride. In a preferred embodiment, silicondioxide is used as the insulating material. The silicon dioxide can bedeposited using any known process, such as CVD or HDPCVD.

Next the dielectric material on top of the pillars 300 is removed,exposing the tops of pillars 300 separated by dielectric material 108,and leaving a substantially planar surface. This removal of dielectricoverfill and planarization can be performed by any process known in theart, such as CMP or etchback. For example, the etchback techniquesdescribed in the '417 application can be used. The resulting structureis shown in FIG. 13B.

Turning to FIG. 13C, in preferred embodiments, heavily doped top regions116 are formed at this point by ion implantation with a p-type dopant,for example boron or BF₂. The diode described herein has a bottom n-typeregion and a top p-type region. If preferred, the conductivity typescould be reversed. If desired, p-i-n diodes having an n-region on thebottom could be used in one memory level while p-i-n diodes having ap-type region on the bottom could be used in another memory level.

The diodes that reside in pillars 300 were formed by a method comprisingdepositing a semiconductor layer stack above the first conductors anddielectric fill; and patterning and etching the semiconductor layerstack to form the first diodes.

Next a layer 121 of a conductive barrier material, for example titaniumnitride, a metal, or some other appropriate material, is deposited. Thethickness of layer 121 may be between about 100 and about 400 angstroms,preferably about 200 angstroms. In some embodiments, layer 121 may beomitted.

A layer 118 of a metal oxide or nitride resistance-switching material isdeposited on barrier layer 121. This layer is preferably between about50 and about 400 angstroms, for example between about 100 and about 200angstroms. Layer 118 can be any of the materials described earlier, andis preferably formed of a metal oxide or nitride having includingexactly one metal which exhibits resistance switching behavior;preferably a material selected from the group consisting of Ni_(x)O_(y),Nb_(x)O_(y), Ti_(x)O_(y), Hf_(x)O_(y), Al_(x)O_(y), Mg_(x)O_(y),Co_(x)O_(y), Cr_(x)O_(y), V_(x)O_(y), Zn_(x)O_(y), Zr_(x)O_(y),B_(x)N_(y), and Al_(x)N_(y).

For simplicity this discussion will describe the use of nickel oxide inlayer 118. It will be understood, however, that any of the othermaterials described can be used. nickel oxide exhibits nondirectionalswitching behavior, and thus has been paired with a p-i-n diode, thougha Zener diode could have been used had the circuit arrangement dictatedsuch a choice.

As described earlier, had a directional resistance switching materialbeen selected, a Zener diode would have been preferred. In a preferredembodiment, such a Zener diode has no intrinsic region, or has anintrinsic region no thicker than about 350 angstroms.

Finally in preferred embodiments barrier layer 123 is deposited onnickel oxide layer 118. Layer 123 is preferably titanium nitride, thoughsome other appropriate conductive barrier material may be used instead.The purpose of barrier layer 123 is to allow an upcoming planarizationstep to be performed on barrier layer 123 rather than nickel oxide layer118. In some embodiments, layer 123 may be omitted.

Layers 123, 118, and 121 are patterned and etched to form short pillars,ideally directly on top of pillars 300 formed in the previous patternand etch step. Some misalignment may occur, as shown in FIG. 13C, andcan be tolerated. The photomask used to pattern pillars 300 may bereused in this patterning step.

In this example, layers 123, 118, and 121 were patterned in a differentpatterning step than germanium layers 112 and 114 (and 116, formed in asubsequent ion implantation step.) This may be desirable in order toreduce etch height and to avoid possible contamination by having nickeloxide and metal barrier layers exposed in a chamber devoted tosemiconductor etch.

In other embodiments, however, it may be preferred to pattern layers123, 118, 121, 116, 114, and 112 in a single patterning step. In thiscase the ion implantation of heavily doped germanium layer 116 takesplace before the deposition of barrier layer 121. Alternatively, heavilydoped layer 116 may be in situ doped.

In some embodiments, barrier layer 121, nickel oxide layer 118, andbarrier layer 123 can be formed before (and therefore beneath) diodelayers 112, 114, and 116, and may be patterned in the same or in aseparate patterning step.

Next a conductive material or stack is deposited to form the topconductors 400. In a preferred embodiment, titanium nitride barrierlayer 120 is deposited next, followed by aluminum layer 122 and toptitanium nitride barrier layer 124.

Top conductors 400 can be patterned and etched as described earlier. Inthis example in each cell the diode (of layers 112, 114, and 116) and aresistance-switching element (a portion of nickel oxide layer 118) havebeen formed in series between top conductor 400 and bottom conductor200.

Overlying second conductors 400 will preferably extend in a differentdirection from first conductors 200, preferably substantiallyperpendicular to them. The resulting structure, shown in FIG. 13C, is abottom or first story of memory cells.

In an alternative embodiment, top conductors can comprise copper, andcan be formed by a damascene method. A detailed description offabrication of top copper conductors in a monolithic three dimensionalmemory array is provided in detail in U.S. patent application Ser. No.11/125,606, “High-Density Nonvolatile Memory Array Fabricated at LowTemperature Comprising Semiconductor Diodes.”

In preferred embodiments, this first story of memory cells is aplurality of nonvolatile memory cells comprising: a first plurality ofsubstantially parallel, substantially coplanar conductors extending in afirst direction; a first plurality of diodes; a first plurality ofreversible resistance-switching elements; and a second plurality ofsubstantially parallel, substantially coplanar conductors extending in asecond direction different from the first direction, wherein, in eachmemory cell, one of the first diodes and one of the first reversibleresistance-switching elements are arranged in series, disposed betweenone of the first conductors and one of the second conductors, andwherein the first plurality of reversible resistance-switching elementscomprise a material selected from the group consisting of Ni_(x)O_(y),Nb_(x)O_(y), Ti_(x)O_(y), Hf_(x)O_(y), Al_(x)O_(y), Mg_(x)O_(y),Co_(x)O_(y), Cr_(x)O_(y), V_(x)O_(y), Zn_(x)O_(y), Zr_(x)O_(y),B_(x)N_(y), and Al_(x)N_(y). The first conductors are formed at a firstheight and the second conductors are formed at a second height, thesecond height above the first height.

Additional memory levels can be formed above this first memory level. Insome embodiments, conductors can be shared between memory levels; i.e.top conductor 400 would serve as the bottom conductor of the next memorylevel.

In other embodiments, an interlevel dielectric is formed above the firstmemory level of FIG. 13C, its surface planarized, and construction of asecond memory level begins on this planarized interlevel dielectric,with no shared conductors. If top conductors 400 are not shared betweenmemory levels, then no CMP step need be performed on these conductors.In this case, if desired, titanium nitride barrier layer 124 may bereplaced with a layer of DARC.

Deposited germanium, when undoped or doped with n-type dopants anddeposited at a relatively low temperature, as described, will generallybe amorphous. After all of the memory levels have been constructed, afinal relatively low-temperature anneal, for example performed atbetween about 350 and about 470° C., can be performed to crystallize thegermanium diodes; in this embodiment the resulting diodes will be formedof polygermanium. Large batches of wafers, for example 100 wafers ormore, can be annealed at a time, maintaining adequate manufacturingthroughput.

Vertical interconnects between memory levels and between circuitry inthe substrate are preferably formed as tungsten plugs, which can beformed by any conventional method.

Photomasks are used during photolithography to pattern each layer.Certain layers are repeated in each memory level, and the photomasksused to form them may be reused. For example, a photomask defining thepillars 300 of FIG. 13C may be reused for each memory level. Eachphotomask includes reference marks used to properly align it. When aphotomask is reused, reference marks formed in a second or subsequentuse may interfere with the same reference marks formed during a prioruse of the same photomask.

U.S. patent application Ser. No. 11/097,496, “Masking of RepeatedOverlay and Alignment Marks to Allow Reuse of Photomasks in a VerticalStructure,” filed Mar. 31, 2005, and hereby incorporated by reference,describes a method to avoid such interference during the formation of amonolithic three dimensional memory array like that of the presentinvention.

Many variations on the steps and structures described here can beenvisioned and may be desirable. To more fully illustrate the presentinvention, a few variations will be described; it will be understoodthat not every variation that falls within the scope of the inventionneed be fully detailed for those skilled in the art to understand how tomake and use a still broader range of possible variations.

SECOND FABRICATION EXAMPLE Noble Metal Contacts, Above Diode

FIG. 10 showed an embodiment in which resistance-switching material 118was sandwiched between noble metal layers 117 and 119. Preferred noblemetals are Pt, Pd, Ir and Au. Layers 117 and 119 may be formed of thesame noble metal, or of different metals.

When the resistance switching material is sandwiched between noble metallayers, the noble metal layers must be patterned and etched to assurethat they do not provide unwanted conductive paths between adjacentdiodes or conductors.

A memory level comprising cells like those of FIG. 10 is shown incross-section in FIG. 14. In a preferred method to form this structure,bottom conductor 200 is formed as described earlier. Heavily dopedgermanium layer 112 and undoped germanium layer 114 are deposited asdescribed earlier.

In one preferred embodiment, the ion implantation of top heavily dopedlayer 116 can be performed on the blanket germanium layer before thepillars are patterned and etched. Next noble metal layer 117 isdeposited, followed by resistance-switching material 118 and noble metallayer 119. Noble metal layers 117 and 119 may be about 200 to about 500angstroms, preferably about 200 angstroms.

The pillars are patterned and etched at this point, such that layers117, 118, and 119 are included in the pillar, and thus are electricallyisolated from each other. Depending on the etchants selected, it may bepreferred to perform a first etch step, etching only layers 119, 118,and 117, then use these layers as a hard mask to etch the rest of thepillar.

Alternatively, layers 112, 114, and 116 may be patterned and etched,gaps between them filled, and tops of the pillars exposed throughplanarization first. Deposition of layers 117, 118, and 119 couldfollow, along with separate pattern and etch of those layers.

The gaps are filled and a CMP or etchback step performed as describedearlier to create a substantially planar surface. Next top conductors400 are formed on this planar surface as described earlier, comprising atitanium nitride layer 120, aluminum layer 122, and titanium nitridelayer 124. Alternatively, top noble metal layer 119 could be deposited,patterned and etched with top conductors 400.

In another alternative, heavily doped layer 116 could be doped byin-situ doping rather than by ion implantation.

THIRD FABRICATION EXAMPLE Noble Metal Contacts, Below Diode

In an alternative embodiment, shown in FIG. 15, the resistance-switchingelements 118, in this case sandwiched between noble metal layers 117 and119, are formed below the diode, rather than above it.

To form this structure, bottom conductors 200 are formed as describedearlier. Layers 117, 118, and 119 are deposited on the planarizedsurface 109 of conductors 200 separated by gap fill. The germaniumstack, including heavily doped layer 112 and undoped layer 114, aredeposited. Layers 114, 112, 119, 118, and optionally 117 are patternedand etched as described earlier to form pillars 300.

After gap fill and planarization, top heavily doped region 116 is formedby ion implantation. Top conductors 400 are formed as in the previousembodiment, by depositing conductive layers, for example titaniumnitride layer 120, aluminum layer 122, and titanium nitride layer 124,and patterning and etching to form the conductors 400.

As in other embodiments, if desired, layers 117, 118, and 119 could bepatterned and etched separately from layers 110, 112, 114, and 116rather than etching them all in a single patterning step.

In the preferred embodiments just described, what has been formed is amonolithic three dimensional memory array comprising: a) a first memorylevel formed above a substrate, the first memory level comprising: afirst plurality of memory cells, wherein each memory cell of the firstmemory comprises a reversible resistance-switching element comprising amaterial selected from the group consisting of Ni_(x)O_(y), Nb_(x)O_(y),Ti_(x)O_(y), Hf_(x)O_(y), Al_(x)O_(y), Mg_(x)O_(y), Co_(x)O_(y),Cr_(x)O_(y), V_(x)O_(y), Zn_(x)O_(y), Zr_(x)O_(y), B_(x)N_(y), andAl_(x)N_(y); and b) at least a second memory level monolithically formedabove the first memory level.

Many other alternative embodiments can be imagined. For example, in someembodiments the noble metal layers 117 and 119 can be omitted. In thiscase resistance-switching material 118 can be patterned with bottomconductors 200, with pillars 300, or left as a continuous layer above orbelow the diodes.

An advantage of the embodiments just described is that use of germaniumin the diode allows formation of a nonvolatile memory cell by forming afirst conductor; forming a second conductor; forming a reversibleresistance-switching element; and forming a diode, wherein the diode andthe reversible resistance-switching element are disposed electrically inseries between the first conductor and the second conductor, andwherein, during formation of the first and second conductors, diode, andswitching element and crystallization of the diode, temperature does notexceed about 500° C.

Depending on the deposition and crystallization conditions used (alonger crystallizing anneal can be performed at lower temperatures), thetemperature may not exceed about 350° C. In alternative embodiments, thedeposition and crystallization temperatures of the semiconductormaterial may be arranged so that the maximum temperature does not exceed475, 425, 400, or 375° C.

FOURTH FABRICATION EXAMPLE Silicided Diode

It may be preferred to form the diode of silicon, specifically ofpolysilicon crystallized adjacent to a silicide that may provide anadvantageous crystallization template, such as titanium silicide orcobalt silicide, forming relatively low-defect, low-resistivitypolysilicon.

Referring to FIG. 16A, bottom conductors 200 can be formed as describedearlier. Polysilicon generally requires a crystallization temperatureincompatible with copper and aluminum, so a material able to toleratehigh temperature, such as tungsten, may be the preferred conductivematerial 106 for bottom conductors 200.

In a preferred embodiment, adhesion layer 104 is deposited first,followed by tungsten layer 106, and these layers are patterned andetched to form substantially parallel conductors 200. Dielectric fill108 is deposited over and between conductors 200, then a planarizationstep, for example by CMP, removes overfill, leaving conductors 200 anddielectric 108 exposed at a substantially planar surface.

Next a thin barrier layer 110, for example of titanium nitride, isdeposited on the planar surface. Next the semiconductor material thatwill form the diode is deposited. In the present embodiment, thesemiconductor material is preferably silicon or a silicon-richsilicon-germanium alloy. Heavily doped n-type region 112 is depositedfirst, preferably doped by in situ doping. This layer may be betweenabout 100 and about 1000 angstroms thick, preferably about 200angstroms.

Next intrinsic silicon is deposited, preferably to a thickness betweenabout 800 and about 3300 angstroms. Heavily doped p-type region 116 atthe top of the silicon stack is doped, preferably by ion implantation ofa p-type dopant such as boron or BF₂, leaving middle region 114 undoped.In an alternative embodiment, heavily doped p-type region 116 is dopedin situ.

A thin layer 125 of titanium, for example between about 50 and about 200angstroms, is deposited. An optional barrier layer 121 is depositednext, followed by nickel oxide layer 118 (any of the other namedresistivity-switching metal oxides or nitrides could be used instead)and optional top barrier layer 123, which may be of titanium nitride.The layer 118 of nickel oxide may include added metal, as described inthe '452 application, which may serve to reduce switching voltages orcurrents and to reduce or eliminate the need for a forming pulse.

Barrier layer 123, nickel oxide layer 118, and barrier layer 121 arepatterned and etched to form short pillars. Layer 118 of nickel oxidecan be sputter etched, or is preferably etched using a chemical processas described in U.S. patent application Ser. No. 11/179,423, “Method ofPlasma Etching Transition Metals and Their Compounds,” filed Jun. 11,2005 and hereby incorporated by reference. The structure at this pointis shown in FIG. 16A.

Turning to FIG. 16B, the etch continues, with etched layers 121, 118,and 123 serving as a hard mask during the etch of titanium layer 125,heavily doped p-type region 116, intrinsic region 114, heavily dopedn-type region 112, and barrier layer 110, forming pillars 300.Dielectric material 108 is deposited over and between pillars 300,filling gaps between them.

A planarization step, for example by CMP, removes overfill of dielectric108 and exposes optional barrier layer 123 (or, if barrier layer 123 wasomitted, nickel oxide layer 118) at the tops of pillars 300, separatedby fill 108. FIG. 16B shows the structure at this point.

Referring to FIG. 16C, top conductors 400 are preferably formed as inprior embodiments, for example of adhesion layer 120 of titanium nitrideand conductive layer 130 of tungsten.

An anneal step causes titanium layer 125 to react with silicon region116, forming titanium silicide. A subsequent higher temperature annealcrystallizes the silicon of silicon regions 116, 114, and 112, forming adiode of relatively low-defect, low-resistivity polysilicon.

Many variations are possible in forming this memory cell. For example,if preferred, nickel oxide layer 118 and any associated barrier layerscan be patterned and etched in a separate step, rather than in the samepatterning step that forms the diode.

FIFTH FABRICATION EXAMPLE Non-Silicided Diode

It was noted that in one-time-programmable embodiments which use theresistivity state of the polysilicon of the diode to store a data state,it may be preferred to form a polysilicon diode which is notcrystallized adjacent to a silicide that promotes formation oflow-defect polysilicon.

In this case, the bottom conductors 200 are formed as described above.Pillars 300 are formed as described in the prior, silicided embodiment,with the exception that titanium layer 125, which in that embodimentreacted with silicon of the diode to form titanium silicide, is omitted.Layer 118 of nickel oxide and any associated barrier layers arepreferably patterned and etched first, then serve as a hard mask to etchsilicon regions 116, 114, and 112 and barrier layer 110.

Alternatively, diode layers 116, 114, and 112 can be patterned andetched first, gaps between them filled with dielectric and tops of thediodes exposed in a planarizing step, then nickel oxide layer 118 andits associated barrier layers deposited, then patterned and etched in aseparate step.

As in all embodiments, a first story of memory cells has been formed.Additional memory levels may be stacked above this first memory level toform a monolithic three dimensional memory array, preferably formedabove a semiconductor substrate.

One-time programmable monolithic three dimensional memory arrays aredescribed in U.S. Pat. No. 6,034,882, “Vertically Stacked FieldProgrammable Nonvolatile Memory and Method of Fabrication,” U.S. Pat.No. 6,420,215, “Three Dimensional Memory Array and Method ofFabrication,” and U.S. patent application Ser. No. 10/185,507,“Electrically Isolated Pillars in Active Devices,” filed Jun. 27, 2002,all assigned to the assignee of the present invention and herebyincorporated by reference.

A monolithic three dimensional memory array is one in which multiplememory levels are formed above a single substrate, such as a wafer, withno intervening substrates. The layers forming one memory level aredeposited or grown directly over the layers of an existing level orlevels. In contrast, stacked memories have been constructed by formingmemory levels on separate substrates and adhering the memory levels atopeach other, as in U.S. Pat. No. 5,915,167, “Three dimensional structurememory.” The substrates may be thinned or removed from the memory levelsbefore bonding, but as the memory levels are initially formed overseparate substrates, such memories are not true monolithic threedimensional memory arrays.

A monolithic three dimensional memory array formed above a substratecomprises at least a first memory level formed at a first height abovethe substrate and a second memory level formed at a second heightdifferent from the first height. Three, four, eight, or indeed anynumber of memory levels can be formed above the substrate in such amultilevel array.

Detailed methods of fabrication have been described herein, but anyother methods that form the same structures can be used while theresults fall within the scope of the invention.

The foregoing detailed description has described only a few of the manyforms that this invention can take. For this reason, this detaileddescription is intended by way of illustration, and not by way oflimitation. It is only the following claims, including all equivalents,which are intended to define the scope of this invention.

1. A nonvolatile memory cell comprising: a diode; and a reversibleresistance-switching element comprising a resistance-switching metaloxide or nitride, the metal oxide or nitride comprising only one metal.2. The nonvolatile memory cell of claim 1, wherein the metal oxide ornitride comprises one or more of Ni_(x)O_(y), Nb_(x)O_(y), Ti_(x)O_(y),Hf_(x)O_(y), Al_(x)O_(y), Mg_(x)O_(y), Co_(x)O_(y), Cr_(x)O_(y),V_(x)O_(y), Zn_(x)O_(y), Zr_(x)O_(y), B_(x)N_(y), and Al_(x)N_(y). 3.The nonvolatile memory cell of claim 1, wherein the metal oxide ornitride comprises one or more of NiO, Nb₂O₅, TiO₂, HfO₂, Al₂O₃, MgO_(x),CrO₂, VO, BN, and AlN.
 4. The nonvolatile memory cell of claim 1,wherein the diode and the reversible resistance-switching element arecoupled in series.
 5. The nonvolatile memory cell of claim 1, whereinthe diode is above or below the reversible resistance-switching element.6. The nonvolatile memory cell of claim 1, wherein the diode comprises avertically oriented pillar.
 7. The nonvolatile memory cell of claim 1,wherein the diode comprises a semiconductor junction diode.
 8. Thenonvolatile memory cell of claim 7, wherein the semiconductor junctiondiode is vertically oriented, comprising a bottom heavily doped regionhaving a first conductivity type, a middle intrinsic or lightly dopedregion, and a top heavily doped region having a second conductivitytype.
 9. The nonvolatile memory cell of claim 1, wherein the reversibleresistance-switching element comprises a pillar.
 10. The nonvolatilememory cell of claim 1, wherein the memory cell comprises a first memorylevel.
 11. The nonvolatile memory cell of claim 10, wherein the firstmemory level is formed above a monocrystalline silicon substrate. 12.The nonvolatile memory cell of claim 10, wherein at least a secondmemory level is monolithically formed above the first memory level. 13.The nonvolatile memory cell of claim 1, wherein the memory cell isrewriteable.
 14. The nonvolatile memory cell of claim 1, wherein thediode and the reversible resistance-switching element are disposedbetween a first conductor and a second conductor.
 15. The nonvolatilememory cell of claim 14, wherein the second conductor is above the firstconductor, and the diode and the resistance-switching element arevertically disposed between them.
 16. The nonvolatile memory cell ofclaim 14, wherein the first conductor and the second conductor arerail-shaped.
 17. The nonvolatile memory cell of claim 9, wherein thefirst conductor extends in a first direction and the second conductorextends in a second direction different from the first direction.
 18. Amonolithic three-dimensional memory array comprising the nonvolatilememory cell of claim
 1. 19. A monolithic three-dimensional memory arraycomprising a first memory level comprising a plurality of thenonvolatile memory cells of claim
 1. 20. A monolithic three-dimensionalmemory array comprising: a first memory level comprising a plurality ofthe nonvolatile memory cells of claim 1; and a second memory levelcomprising a plurality of the nonvolatile memory cells of claim 1, thesecond memory level disposed above the first memory level.